Formation of semiconductor structures with variable gate lengths

Invention Grant

US08999791B2 Formation of semiconductor structures with variable gate lengths 有权

Title translation: 形成具有可变栅极长度的半导体结构

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Patent Title: Formation of semiconductor structures with variable gate lengths
Patent Title (中): 形成具有可变栅极长度的半导体结构
Application No.: US13886909

Application Date: 2013-05-03
Publication No.: US08999791B2

Publication Date: 2015-04-07
Inventor: Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
Applicant: International Business Machines Corporation
Applicant Address: US NY Armonk
Assignee: International Business Machines Corporation
Current Assignee: International Business Machines Corporation
Current Assignee Address: US NY Armonk
Agency: Scully, Scott, Murphy & Presser, P.C.
Agent Daniel P. Morris, Esq.
Main IPC: H01L21/8234
IPC: H01L21/8234 ; H01L21/28 ; H01L29/66

Formation of semiconductor structures with variable gate lengths

Abstract:

A plurality of doped sacrificial semiconductor material portions of a first width and a plurality of doped sacrificial semiconductor material portions of a second width, which is different from the first width, are provided on a sacrificial gate dielectric material. Exposed portions of the sacrificial dielectric material are removed. A dielectric material is formed adjacent each doped sacrificial semiconductor material portion such that an upper surface of each doped sacrificial semiconductor material portion is exposed. Each doped sacrificial semiconductor material portion is removed providing a first set of gate cavities having the first width and a second set of gate cavities having the second width. Each gate cavity is filled with a gate structure. The gate structures formed in the first set of gate cavities have the first width, while the gate structure formed in the second set of gate cavities have the second width.

Abstract(Chinese):

在牺牲栅极电介质材料上设置有第一宽度的多个掺杂牺牲半导体材料部分和与第一宽度不同的第二宽度的多个掺杂牺牲半导体材料部分。除去牺牲绝缘材料的暴露部分。在每个掺杂的牺牲半导体材料部分附近形成介电材料，使得每个掺杂的牺牲半导体材料部分的上表面被暴露。去除每个掺杂的牺牲半导体材料部分，提供具有第一宽度的第一组栅极腔和具有第二宽度的第二组栅极腔。每个门腔填充有栅极结构。形成在第一组栅极腔中的栅极结构具有第一宽度，而形成在第二组栅极腔中的栅极结构具有第二宽度。

Public/Granted literature

US20140329380A1 FORMATION OF SEMICONDUCTOR STRUCTURES WITH VARIABLE GATE LENGTHS Public/Granted day:2014-11-06

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺