Invention Grant
- Patent Title: Method of making a stacked microelectronic package
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Application No.: US13970028Application Date: 2013-08-19
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Publication No.: US08999810B2Publication Date: 2015-04-07
- Inventor: Belgacem Haba , Vage Oganesian
- Applicant: Tessera, Inc.
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L21/306
- IPC: H01L21/306 ; H01L23/48 ; H01L23/00 ; H01L25/065 ; H01L25/00

Abstract:
A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.
Public/Granted literature
- US20130330905A1 EDGE CONNECT WAFER LEVEL STACKING Public/Granted day:2013-12-12
Information query
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