Invention Grant
US09000532B2 Vertical PMOS field effect transistor and manufacturing method thereof
有权
垂直PMOS场效应晶体管及其制造方法
- Patent Title: Vertical PMOS field effect transistor and manufacturing method thereof
- Patent Title (中): 垂直PMOS场效应晶体管及其制造方法
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Application No.: US14316972Application Date: 2014-06-27
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Publication No.: US09000532B2Publication Date: 2015-04-07
- Inventor: Hsin-Huei Chen , Chung-Yuan Lee
- Applicant: Inotera Memories, Inc.
- Applicant Address: TW Taoyuan County
- Assignee: Inotera Memories, Inc.
- Current Assignee: Inotera Memories, Inc.
- Current Assignee Address: TW Taoyuan County
- Agency: Rosenberg, Klein & Lee
- Priority: TW98141479A 20091204
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L29/78 ; H01L29/10 ; H01L29/165 ; H01L29/66 ; H01L21/28 ; H01L29/161

Abstract:
A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.
Public/Granted literature
- US20140306269A1 VERTICAL PMOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF Public/Granted day:2014-10-16
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