Invention Grant
- Patent Title: Device and methods for high-K and metal gate stacks
- Patent Title (中): 高K和金属栅极堆叠的器件和方法
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Application No.: US13457079Application Date: 2012-04-26
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Publication No.: US09000533B2Publication Date: 2015-04-07
- Inventor: Wei Cheng Wu , Po-Nien Chen , Jin-Aun Ng , Bao-Ru Young , Harry-Hak-Lay Chuang
- Applicant: Wei Cheng Wu , Po-Nien Chen , Jin-Aun Ng , Bao-Ru Young , Harry-Hak-Lay Chuang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L21/8238 ; H01L27/06 ; H01L29/51
Abstract:
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.
Public/Granted literature
- US20130285151A1 DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS Public/Granted day:2013-10-31
Information query
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