Invention Grant
- Patent Title: Wafer-level thin chip integration
- Patent Title (中): 晶圆级薄片集成
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Application No.: US13930439Application Date: 2013-06-28
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Publication No.: US09000587B1Publication Date: 2015-04-07
- Inventor: Amit S. Kelkar , Vivek S. Sridharan
- Applicant: Maxim Integrated Products, Inc.
- Applicant Address: US CA San Jose
- Assignee: Maxim Integrated Products, Inc.
- Current Assignee: Maxim Integrated Products, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Advent, LLP
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/60 ; H01L25/00
Abstract:
A wafer-level package device and techniques for fabricating the device are described that include embedding a silicon chip onto an active device wafer or a passive device wafer, where the embedded silicon chip is a thin chip (e.g.,
Information query
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