A digital-to-analog converter includes a first decoder, a second decoder and a voltage summing buffer. The first decoder receives upper bits of a digital signal and upper reference voltages to output an upper voltage corresponding to the upper bits. The second decoder configured to receive lower bits of the digital signal and lower reference voltages to output a lower differential voltage corresponding to the lower bits. The voltage summing buffer generates an output voltage based on the upper voltage and the lower differential voltage, such that the output voltage corresponds to the digital signal including the upper bits and the lower bits.