Invention Grant
- Patent Title: Blocking current leakage in a memory array
- Patent Title (中): 阻塞存储器阵列中的电流泄漏
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Application No.: US13458644Application Date: 2012-04-27
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Publication No.: US09001550B2Publication Date: 2015-04-07
- Inventor: Hsiang-Lan Lung
- Applicant: Hsiang-Lan Lung
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; H01L45/00 ; G11C17/06 ; G11C29/00 ; G11C13/00 ; G11C29/08 ; G11C29/44

Abstract:
A method for blocking current leakage through defective memory cells in a memory array is provided. The memory cells include access devices and programmable resistance memory elements. The method includes identifying addresses of defective memory cells in the memory array, and applying a modifying bias condition to modify the defective memory cells at the identified addresses. The modifying bias condition causes the defective memory cells to transform into a current blocking condition. The method also includes storing the identified addresses in a redundancy table of addresses. An automatic test system includes a device tester adapted to identify addresses of defective memory cells in a memory array in an integrated circuit under test, and to apply a modifying bias condition to modify the defective memory cells at the identified addresses.
Public/Granted literature
- US20130286711A1 BLOCKING CURRENT LEAKAGE IN A MEMORY ARRAY Public/Granted day:2013-10-31
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