A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.