Invention Grant
US09001582B2 Nonvolatile semiconductor memory device having a column decoder with multiple data bus portions connected via a switch
有权
具有通过开关连接多个数据总线部分的列解码器的非易失性半导体存储器件
- Patent Title: Nonvolatile semiconductor memory device having a column decoder with multiple data bus portions connected via a switch
- Patent Title (中): 具有通过开关连接多个数据总线部分的列解码器的非易失性半导体存储器件
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Application No.: US13784658Application Date: 2013-03-04
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Publication No.: US09001582B2Publication Date: 2015-04-07
- Inventor: Tomofumi Fujimura , Naofumi Abiko
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2012-065148 20120322
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/06 ; G11C16/24 ; G11C16/26 ; G11C11/56
Abstract:
A nonvolatile semiconductor memory device includes memory cells arranged into memory strings with word lines each connected to a different memory cell of the memory strings. The device also includes bit lines each connected to a different memory string and a column decoder connected to the bit lines. The column decoder includes sense amplifiers, data latches, and a data bus connecting sense amplifiers and data latches. The data bus is divided into at least two portions and includes a first portion connected to a second portion by a switch.
Public/Granted literature
- US20130250684A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2013-09-26
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