A semiconductor device including multiple subarrays arrayed in a matrix in the row and column directions, and respectively containing multiple memory cells, bit lines coupled to the memory cells, and precharge circuits (to charge the bit lines; column select signal lines extending in the column direction for selecting subarray columns; main word lines for selecting subarray rows; and precharge signal lines for supplying precharge signals to the precharge circuits; and at least two of the subarrays formed in the row direction or the column direction are controlled by the same logic according to the precharge signal.