Invention Grant
- Patent Title: Method of burn-in test of EEPROM or flash memories
- Patent Title (中): EEPROM或闪存的老化测试方法
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Application No.: US13610443Application Date: 2012-09-11
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Publication No.: US09001602B2Publication Date: 2015-04-07
- Inventor: Francois Tailliet
- Applicant: Francois Tailliet
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Seed IP Law Group PLLC
- Priority: FR1158095 20110912
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/02 ; G11C29/06

Abstract:
A method for testing an integrated circuit includes, in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage. The first test voltage is set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down. The second test voltage is set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps.
Public/Granted literature
- US20130064015A1 METHOD OF BURN-IN TEST OF EEPROM OR FLASH MEMORIES Public/Granted day:2013-03-14
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