Invention Grant
- Patent Title: Method of overlapping interconnect signal lines for reducing capacitive coupling effects
- Patent Title (中): 用于减少电容耦合效应的互连信号线重叠方法
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Application No.: US14287890Application Date: 2014-05-27
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Publication No.: US09001605B2Publication Date: 2015-04-07
- Inventor: David V. Carlson
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Gardere Wynne Sewell LLP
- Main IPC: G11C7/02
- IPC: G11C7/02 ; H01L23/522 ; H01L23/528 ; H01L21/82 ; H01L21/8234

Abstract:
Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.
Public/Granted literature
- US20140254292A1 OVERLAPPING INTERCONNECT SIGNAL LINES FOR REDUCING CAPACITIVE COUPLING EFFECTS Public/Granted day:2014-09-11
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