A phase interpolation circuit includes: a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals; a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals; and a third circuit configured to generate an output signal by combining the first intermediate signal and the second intermediate signal.