Invention Grant
US09001954B2 Reception circuit, information processing device, and buffer control method
有权
接收电路,信息处理装置和缓冲器控制方法
- Patent Title: Reception circuit, information processing device, and buffer control method
- Patent Title (中): 接收电路,信息处理装置和缓冲器控制方法
-
Application No.: US13009661Application Date: 2011-01-19
-
Publication No.: US09001954B2Publication Date: 2015-04-07
- Inventor: Ryuji Iwatsuki , Kazumi Hayasaka
- Applicant: Ryuji Iwatsuki , Kazumi Hayasaka
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2010-012341 20100122
- Main IPC: H04L25/00
- IPC: H04L25/00 ; H04L7/08 ; H04L25/14

Abstract:
A reception circuit that receives data in serial communications through a plurality of lanes includes a plurality of buffers provided for each of the plurality of lanes that each stores data received through corresponding lane, a multilane control circuit that detects the skew between the lanes, and outputs an adjustment instruction for adjusting a read address of a buffer and a deskew information indicating that a skew adjustment between which buffer the lanes is to be performed based on the detected skew, and a plurality of address control circuits provided for each of the plurality of lanes that each transmits the adjustment instruction to a corresponding buffer when receiving the deskew information, wherein the buffer that has received the adjustment instruction adjusting its read address.
Public/Granted literature
- US20110182384A1 RECEPTION CIRCUIT, INFORMATION PROCESSING DEVICE, AND BUFFER CONTROL METHOD Public/Granted day:2011-07-28
Information query