Invention Grant
- Patent Title: Stable parallel loop systems
- Patent Title (中): 稳定并联回路系统
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Application No.: US13295013Application Date: 2011-11-11
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Publication No.: US09002765B1Publication Date: 2015-04-07
- Inventor: Muralidhar Ravuri
- Applicant: Muralidhar Ravuri
- Agency: Spano Law Group
- Agent Joseph S. Spano
- Main IPC: G06N3/04
- IPC: G06N3/04 ; G06N3/08

Abstract:
Stable Parallel Loop (SPL) systems and exemplary embodiments are described with reference to both software and hardware platforms. A SPL network includes an input surface, internal nodes, connections that selectively link internal nodes, and an output surface. Signals from the environment are received on the input surface. The received signals excite internal nodes of the SPL network. The internal nodes exhibit their own dynamic behavior. As a result of the interconnected network structure and operational characteristics of each node, dynamic loops are formed among certain internal nodes. A dynamic loop is formed when all of internal nodes within an interconnected loop are active. Output from the SPL network is generated based on the dynamic loops that are formed. Tools to develop and implement a SPL network are presented.
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