Invention Grant
US09003125B2 Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index
有权
缓存一致性协议,用于允许并行数据提取和迁出到相同的可寻址索引
- Patent Title: Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index
- Patent Title (中): 缓存一致性协议,用于允许并行数据提取和迁出到相同的可寻址索引
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Application No.: US13523535Application Date: 2012-06-14
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Publication No.: US09003125B2Publication Date: 2015-04-07
- Inventor: Ekaterina M. Ambroladze , Michael Blake , Tim Bronson , Garrett Drapala , Pak-kin Mak , Arthur J. O'Neill
- Applicant: Ekaterina M. Ambroladze , Michael Blake , Tim Bronson , Garrett Drapala , Pak-kin Mak , Arthur J. O'Neill
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Margaret McNamara
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.
Public/Granted literature
- US20130339622A1 CACHE COHERENCY PROTOCOL FOR ALLOWING PARALLEL DATA FETCHES AND EVICTION TO THE SAME ADDRESSABLE INDEX Public/Granted day:2013-12-19
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