Invention Grant
- Patent Title: Generating hardware accelerators and processor offloads
- Patent Title (中): 生成硬件加速器和处理器卸载
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Application No.: US13358407Application Date: 2012-01-25
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Publication No.: US09003166B2Publication Date: 2015-04-07
- Inventor: Navendu Sinha , William Charles Jordan , Bryon Irwin Moyer , Stephen John Joseph Fricke , Roberto Attias , Akash Renukadas Deshpande , Vineet Gupta , Shobhit Sonakiya
- Applicant: Navendu Sinha , William Charles Jordan , Bryon Irwin Moyer , Stephen John Joseph Fricke , Roberto Attias , Akash Renukadas Deshpande , Vineet Gupta , Shobhit Sonakiya
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/54
Abstract:
System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.
Public/Granted literature
- US20120124588A1 Generating Hardware Accelerators and Processor Offloads Public/Granted day:2012-05-17
Information query
