Invention Grant
US09003255B2 Automatic test-pattern generation for memory-shadow-logic testing
有权
用于内存阴影逻辑测试的自动测试模式生成
- Patent Title: Automatic test-pattern generation for memory-shadow-logic testing
- Patent Title (中): 用于内存阴影逻辑测试的自动测试模式生成
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Application No.: US13175530Application Date: 2011-07-01
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Publication No.: US09003255B2Publication Date: 2015-04-07
- Inventor: Nishu Kohli
- Applicant: Nishu Kohli
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Gardere Wynne Sewell LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G11C29/00 ; G11C7/00 ; G11C8/00 ; G01R31/3183 ; G11C29/24 ; G11C29/10 ; G11C29/14 ; G11C29/54 ; G11C29/52 ; G11C29/50 ; G11C29/56 ; G11C11/34 ; G11C11/22 ; G11C11/4063
Abstract:
An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.
Public/Granted literature
- US20130007548A1 AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING Public/Granted day:2013-01-03
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