Invention Grant
- Patent Title: Synthesis of clock gated circuit
- Patent Title (中): 时钟门控电路的合成
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Application No.: US14200839Application Date: 2014-03-07
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Publication No.: US09003339B2Publication Date: 2015-04-07
- Inventor: Mark Jensen , Andrew Goodrich , Valery Fouron
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kenyon & Kenyon LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements.
Public/Granted literature
- US20140258948A1 DESIGN SYNTHESIS OF CLOCK GATED CIRCUIT Public/Granted day:2014-09-11
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