Invention Grant
- Patent Title: Lumped aggressor model for signal integrity timing analysis
- Patent Title (中): 用于信号完整性时序分析的集中攻击者模型
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Application No.: US14230931Application Date: 2014-03-31
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Publication No.: US09003342B1Publication Date: 2015-04-07
- Inventor: Igor Keller , Jijun Chen , Dhananjay Griyage
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kenyon & Kenyon LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A lumped aggressor model is used to simulate multiple aggressor nets acting on a victim net. By lumping the aggressor nets together into a single input port, a single voltage excitation may be applied to the input port to simulate the model during static timing analysis. However, a record of each individual aggressor net and several associated attributes for each aggressor net is maintained such that the individual lumped aggressor nets may still be modeled as separate contributions to the attack on the victim net.
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