Invention Grant
- Patent Title: Method of preparing semiconductor layer including cavities
- Patent Title (中): 制备包括空腔的半导体层的方法
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Application No.: US13507210Application Date: 2012-06-13
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Publication No.: US09006084B2Publication Date: 2015-04-14
- Inventor: Shiro Sakai
- Applicant: Shiro Sakai
- Applicant Address: KR Ansan-si
- Assignee: Seoul Viosys Co., Ltd.
- Current Assignee: Seoul Viosys Co., Ltd.
- Current Assignee Address: KR Ansan-si
- Agency: H.C. Park & Associates, PLC
- Priority: JP2009-139212 20090610; JP2009-166682 20090715; JP2009-194334 20090825; JP2010-027650 20100210; JP2010-263008 20101125
- Main IPC: H01L21/46
- IPC: H01L21/46 ; H01L21/02 ; C30B25/02 ; C30B29/40 ; H01L29/20 ; H01L33/00

Abstract:
A method of fabricating a semiconductor substrate, includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, etching the substrate using a solution to remove the metallic material layer and a portion of the first semiconductor layer, and forming a cavity in the first semiconductor layer under where the metallic material layer was removed.
Public/Granted literature
- US20120258559A1 Semiconductor substrate, semiconductor device, and manufacturing methods thereof Public/Granted day:2012-10-11
Information query
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