Invention Grant
- Patent Title: Nanowire transistor devices and forming techniques
- Patent Title (中): 纳米线晶体管器件及成型技术
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Application No.: US13560531Application Date: 2012-07-27
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Publication No.: US09012284B2Publication Date: 2015-04-21
- Inventor: Glenn A. Glass , Kelin J. Kuhn , Seiyon Kim , Anand S. Murthy , Daniel B. Aubertine
- Applicant: Glenn A. Glass , Kelin J. Kuhn , Seiyon Kim , Anand S. Murthy , Daniel B. Aubertine
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/66 ; H01L21/84 ; H01L27/12 ; H01L29/786
Abstract:
Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
Public/Granted literature
- US20130161756A1 NANOWIRE TRANSISTOR DEVICES AND FORMING TECHNIQUES Public/Granted day:2013-06-27
Information query
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