Invention Grant
- Patent Title: III-V semiconductor structures and methods for forming the same
- Patent Title (中): III-V族半导体结构及其形成方法
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Application No.: US13738406Application Date: 2013-01-10
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Publication No.: US09012919B2Publication Date: 2015-04-21
- Inventor: Ed Lindow , Chantal Arena , Ronald Bertram , Ranjan Datta , Subhash Mahajan
- Applicant: SOITEC
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Main IPC: H01L29/20
- IPC: H01L29/20 ; H01L21/02

Abstract:
Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.
Public/Granted literature
- US20130126896A1 III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME Public/Granted day:2013-05-23
Information query
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