A semiconductor memory device includes a compression unit configured to compress a plurality of data, which are read from a memory cell region based on successive read commands and addresses, and to successively output the compressed data during a first test mode, a latching unit configured to latch the compressed data in response to a read strobe signal and to fix the latched value when a fail is detected from the compressed data during the first test mode, and an output unit configured to output the latched value to the outside during a second test mode.