Invention Grant
- Patent Title: Write transaction management within a memory interconnect
- Patent Title (中): 在内存互连中写入事务管理
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Application No.: US13586131Application Date: 2012-08-15
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Publication No.: US09015424B2Publication Date: 2015-04-21
- Inventor: Timothy Charles Mace
- Applicant: Timothy Charles Mace
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08

Abstract:
A memory interconnect between transaction masters and a shared memory. A first snoop request is sent to other transaction masters to trigger them to invalidate any local copy of that data they may hold and for them to return any cached line of data corresponding to the write line of data that is dirty. A first write transaction is sent to the shared memory. When and if any cached line of data is received from the further transaction masters, then the portion data is used to form a second write transaction which is sent to the shared memory and writes the remaining portions of the cached line of data which were not written by the first write transaction in to the shared memory. The serialization circuitry stalls any transaction requests to the write line of data until the first write transaction.
Public/Granted literature
- US20140052933A1 WRITE TRANSACTION MANAGEMENT WITHIN A MEMORY INTERCONNECT Public/Granted day:2014-02-20
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