Invention Grant
US09015451B2 Processor including a cache and a scratch pad memory and memory control method thereof
有权
处理器包括高速缓存和临时存储器及其存储器控制方法
- Patent Title: Processor including a cache and a scratch pad memory and memory control method thereof
- Patent Title (中): 处理器包括高速缓存和临时存储器及其存储器控制方法
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Application No.: US12048658Application Date: 2008-03-14
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Publication No.: US09015451B2Publication Date: 2015-04-21
- Inventor: Il Hyun Park , Soojung Ryu , Dong-Hoon Yoo , Dong Kwan Suh , Jeongwook Kim , Choon Ki Jang
- Applicant: Il Hyun Park , Soojung Ryu , Dong-Hoon Yoo , Dong Kwan Suh , Jeongwook Kim , Choon Ki Jang
- Applicant Address: KR Suwon-si KR Seoul
- Assignee: Samsung Electronics Co., Ltd.,Seoul National University R&DB Foundation
- Current Assignee: Samsung Electronics Co., Ltd.,Seoul National University R&DB Foundation
- Current Assignee Address: KR Suwon-si KR Seoul
- Agency: NSIP Law
- Priority: KR10-2007-0112852 20071106
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F9/38
Abstract:
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.
Public/Granted literature
- US20090119456A1 PROCESSOR AND MEMORY CONTROL METHOD Public/Granted day:2009-05-07
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