A processor having a number of functional units includes a hybrid reset sequence controller that includes a master reset controller that may be configured to hierarchically control a sequence of initialization operations performed on the functional units based upon a value stored within a master control register. In addition, the processor may also include a number of additional controllers, each configured to control initialization operations for a respective functional unit based upon a value stored within an additional respective control register. The master reset controller may control each of the additional reset controllers dependent on the value stored within the master control register.