Invention Grant
- Patent Title: Test techniques and circuitry
- Patent Title (中): 测试技术和电路
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Application No.: US13046620Application Date: 2011-03-11
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Publication No.: US09021323B1Publication Date: 2015-04-28
- Inventor: Jayabrata Gosh Dastidar , Kalyana Ravindra Kantipudi
- Applicant: Jayabrata Gosh Dastidar , Kalyana Ravindra Kantipudi
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Womble, Carlyle, Sandridge & Rice
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/3185

Abstract:
Circuits and a method for testing an integrated circuit (IC) are disclosed. A disclosed circuit block includes a selector circuit that is coupled to receive an enable signal and two clock signals. One of the two clock signals is selected as an output of the selector circuit based on the enable signal received. A storage element is coupled to receive the enable signal and the output of the selector circuit as a clock input signal. A logic gate is coupled to receive the output of the storage element and the enable signal. Another selector circuit is coupled to receive an output from the logic gate and the enable signal. The selector circuit selects either the output from the logic gate or the enable signal as a scan enable signal for a scan chain on the IC.
Information query