Invention Grant
- Patent Title: Lower semiconductor molding die, semiconductor package, and method of manufacturing the semiconductor package
- Patent Title (中): 下半导体成型模，半导体封装以及半导体封装的制造方法
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Application No.: US13785675Application Date: 2013-03-05
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Publication No.: US09024448B2Publication Date: 2015-05-05
- Inventor: Jae-Gwon Jang , Young-Lyong Kim , Ae-Nee Jang
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Onello & Mello, LLP.
- Priority: KR10-2012-0077861 20120717
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/495 ; H01L21/56 ; H01L23/13
Abstract:
A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package.
Public/Granted literature
Information query
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