Invention Grant
- Patent Title: Functional material systems and processes for package-level interconnects
- Patent Title (中): 用于封装级互连的功能材料系统和工艺
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Application No.: US13976192Application Date: 2012-03-29
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Publication No.: US09024453B2Publication Date: 2015-05-05
- Inventor: Rajen S. Sidhu , Ashay A. Dani , Martha A. Dudek
- Applicant: Rajen S. Sidhu , Ashay A. Dani , Martha A. Dudek
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2012/031289 WO 20120329
- International Announcement: WO2013/147808 WO 20131003
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/532 ; H01L23/00 ; H01L21/768

Abstract:
Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package to be tailored, for example based on function. Functional package interconnects may vary one of more of at least material layer composition, layer thickness, number of layers, or a number of materials to achieve a particular function, for example based on an application of the component(s) interconnected or an application of the assembly as a whole. In embodiments, parameters of the multi-layered laminated structures are varied dependent on the interconnect location within an area of a substrate, for example with structures having higher ductility at interconnect locations subject to higher stress.
Public/Granted literature
- US20140225265A1 FUNCTIONAL MATERIAL SYSTEMS AND PROCESSES FOR PACKAGE-LEVEL INTERCONNECTS Public/Granted day:2014-08-14
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