Invention Grant
- Patent Title: Sequential burn-in test mechanism
- Patent Title (中): 顺序老化测试机制
-
Application No.: US13600474Application Date: 2012-08-31
-
Publication No.: US09024647B2Publication Date: 2015-05-05
- Inventor: Arman Vassighi , Victor Zia
- Applicant: Arman Vassighi , Victor Zia
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G01R31/10
- IPC: G01R31/10 ; G01R31/28 ; G01R31/317
Abstract:
A method includes performing a burn-in test on an integrated circuit (IC) by removing power from a first component block within the IC and applying a maximum burn-in voltage and temperature to a second component block within the IC.
Public/Granted literature
- US20140062515A1 Sequential Burn-In Test Mechanism Public/Granted day:2014-03-06
Information query
