Invention Grant
US09024681B2 Signal processing circuit, inverter circuit, buffer circuit, driver circuit, level shifter, and display device
有权
信号处理电路，逆变电路，缓冲电路，驱动电路，电平转换器和显示装置
- Patent Title: Signal processing circuit, inverter circuit, buffer circuit, driver circuit, level shifter, and display device
- Patent Title (中): 信号处理电路，逆变电路，缓冲电路，驱动电路，电平转换器和显示装置
-
Application No.: US13819043Application Date: 2011-08-31
-
Publication No.: US09024681B2Publication Date: 2015-05-05
- Inventor: Yuhichiroh Murakami , Yasushi Sasaki , Etsuo Yamamoto
- Applicant: Yuhichiroh Murakami , Yasushi Sasaki , Etsuo Yamamoto
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Keating & Bennett, LLP
- Priority: JP2010-197197 20100902
- International Application: PCT/JP2011/069824 WO 20110831
- International Announcement: WO2012/029874 WO 20120308
- Main IPC: G05F1/10
- IPC: G05F1/10 ; G05F3/16 ; H04L25/02 ; G09G3/36
Abstract:
A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.
Public/Granted literature
Information query
IPC分类:
