According to one embodiment, a phase change memory includes a memory cell, a select transistor, and a memory cell array. The memory cell includes a chalcogenide wiring, resistance wirings and a cell transistor. The chalcogenide wiring becomes a heater. One end of a plurality of memory cells with sources and drains connected in series is connected to a source of the select transistor. The bit line is connected a drain of the select transistor. The memory cell array is obtained by forming a memory cell string.