Invention Grant
- Patent Title: Metallization scheme for integrated circuit
- Patent Title (中): 集成电路金属化方案
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Application No.: US13651326Application Date: 2012-10-12
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Publication No.: US09025398B2Publication Date: 2015-05-05
- Inventor: Everardo Torres Flores , Hernan A. Castro , Jeremy M. Hirst
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C5/02 ; G11C5/06 ; H01L23/522 ; G11C7/18 ; H01L27/02 ; H01L27/24

Abstract:
For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. Parallel lines in the same metal level can be rotated with respect to one another in adjacent regions, for example to better interface with driver circuitry with orthogonal orientations in the different regions.
Public/Granted literature
- US20140104968A1 METALLIZATION SCHEME FOR INTEGRATED CIRCUIT Public/Granted day:2014-04-17
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