A semiconductor memory device is provided. The semiconductor memory device includes a memory block including a plurality of memory cells; a default refresh controller configured to receive a refresh command from a host, to generate a default refresh signal, and to control the memory cells to be refreshed; and a weak cell refresh controller configured to receive the default refresh signal, to generate a weak cell refresh signal, and to control a weak cell among the memory cells to be refreshed. The weak cell may be refreshed at least one more time during a refresh period during which all of the memory cells are refreshed by the default refresh controller. The semiconductor memory device performs at least one more refresh on a weak cell having a data retention time shorter than a refresh period apart from a normal default refresh, thereby preventing data loss.