Invention Grant
- Patent Title: Router and chip circuit
- Patent Title (中): 路由器和芯片电路
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Application No.: US13645655Application Date: 2012-10-05
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Publication No.: US09025457B2Publication Date: 2015-05-05
- Inventor: Takao Yamaguchi , Atsushi Yoshida , Tomoki Ishii
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: Panasonic Intellectual Property Management Co., Ltd.
- Current Assignee: Panasonic Intellectual Property Management Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: Renner, Otto, Boisselle & Sklar, LLP.
- Priority: JP2010-110478 20100512
- Main IPC: G06F1/32
- IPC: G06F1/32

Abstract:
Routers in a data transfer system relay data between the first node and each of the second nodes. A router includes a load value processing section and an aggregation decision section. The load value processing section obtains information about a load value of another router connected to a communications bus. The load value is a time delay caused by that another router and/or the throughput of that router. The aggregation decision section chooses one of the second nodes at which the data is to be received, and determines a transmission path between the second node chosen and the first node in accordance with information about the load value obtained from each router and information determined during a design process about the number of stages of routers from the first node through each second node and/or the length of data to be transferred.
Public/Granted literature
- US20130028090A1 ROUTER AND CHIP CIRCUIT Public/Granted day:2013-01-31
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