The present disclosure provides a floating-tap decision feedback equalization (DFE) circuit. In an exemplary implementation, the floating-tap DFE circuit may include a high-speed shift register, a deserializer and data selector, a bypass deserializer, a high-speed multiplexer and a tap generation circuit. In one aspect of the invention, the floating-tap DFE circuit may advantageously cover an entire tap range beyond a fixed tap range without holes over a range of data rates. Other embodiments, aspects and features are also disclosed.