Invention Grant
- Patent Title: Expander for loop architectures
- Patent Title (中): 扩展器的循环架构
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Application No.: US13713363Application Date: 2012-12-13
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Publication No.: US09026713B2Publication Date: 2015-05-05
- Inventor: Naresh Madhusudana , Raghavendra Channagiri Nagendra , Giridhar Danayakanakeri
- Applicant: LSI Corporation
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte Ltd
- Current Assignee: Avago Technologies General IP (Singapore) Pte Ltd
- Current Assignee Address: SG Singapore
- Agency: Duft Bornsen & Fettig
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F13/42 ; G06F9/44 ; G06F13/38 ; G06F3/06

Abstract:
An expander for a device architecture, such as a SAS-compatible expander for a SAS architecture, is configured to follow a set of discovery rules that are applied following detection of a discovery-triggering event, such as system power up or reset. According to one of the discovery rules, the expander waits until after a specified duration following the detected discovery-triggering event before passing on, to any other expanders, any requests to check the status of their discovery processing. Using appropriate values for the specified durations for different expanders, the discovery procedure will be performed without any infinite-messaging problems, even when the device architecture has a loop.
Public/Granted literature
- US20140173165A1 Expander for Loop Architectures Public/Granted day:2014-06-19
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