Invention Grant
US09026963B1 System and method for fault sensitivity analysis of mixed-signal integrated circuit designs
有权
混合信号集成电路设计的故障灵敏度分析系统和方法
- Patent Title: System and method for fault sensitivity analysis of mixed-signal integrated circuit designs
- Patent Title (中): 混合信号集成电路设计的故障灵敏度分析系统和方法
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Application No.: US14187794Application Date: 2014-02-24
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Publication No.: US09026963B1Publication Date: 2015-05-05
- Inventor: Donald J. O'Riordan , Ilya Yusim , Zhipeng Liu
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kenyon & Kenyon LLP
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50
Abstract:
An apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.
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