Invention Grant
- Patent Title: Semiconductor integrated circuit partitioning and timing
- Patent Title (中): 半导体集成电路分区和时序
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Application No.: US14140248Application Date: 2013-12-24
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Publication No.: US09026974B2Publication Date: 2015-05-05
- Inventor: Russell B. Segal , Balkrishna R. Rashingkar , Douglas Chang , Mattias A. Hembruch
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Agent Laxman Sahasrabuddhe
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics associated with one or more blocks or one or more flylines can be displayed. Next, in response to receiving a modification to one or more blocks in the graphical representation, the embodiments can update the set of metrics without performing expensive netlist modification, placement, routing, and/or propagation of timing information through multiple levels of logic, and then display the updated set of metrics.
Public/Granted literature
- US20140181776A1 WHAT-IF PARTITIONING AND TIMING Public/Granted day:2014-06-26
Information query