Invention Grant
US09027021B2 Controlling depth and latency of exit of a virtual processor's idle state in a power management environment
有权
在电源管理环境中控制虚拟处理器空闲状态退出的深度和延迟
- Patent Title: Controlling depth and latency of exit of a virtual processor's idle state in a power management environment
- Patent Title (中): 在电源管理环境中控制虚拟处理器空闲状态退出的深度和延迟
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Application No.: US13445051Application Date: 2012-04-12
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Publication No.: US09027021B2Publication Date: 2015-05-05
- Inventor: Richard L. Arndt , Naresh Nayar , Christopher Francois , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg
- Applicant: Richard L. Arndt , Naresh Nayar , Christopher Francois , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Russell Ng PLLC
- Agent Matthew Talpis
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F1/00
Abstract:
A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.
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