Invention Grant
- Patent Title: Gap filling method for dual damascene process
- Patent Title (中): 双镶嵌工艺的间隙填充方法
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Application No.: US13161701Application Date: 2011-06-16
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Publication No.: US09029260B2Publication Date: 2015-05-12
- Inventor: Chun Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
- Applicant: Chun Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L23/532

Abstract:
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
Public/Granted literature
- US20120319278A1 GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS Public/Granted day:2012-12-20
Information query
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