Invention Grant
US09029260B2 Gap filling method for dual damascene process 有权
双镶嵌工艺的间隙填充方法

Gap filling method for dual damascene process
Abstract:
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
Public/Granted literature
Information query
Patent Agency Ranking
0/0