Invention Grant
- Patent Title: Semiconductor memory device and method for manufacturing same
- Patent Title (中): 半导体存储器件及其制造方法
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Application No.: US14204512Application Date: 2014-03-11
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Publication No.: US09029938B2Publication Date: 2015-05-12
- Inventor: Hiroshi Nakaki
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2013-187675 20130910
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L21/336 ; H01L27/115 ; H01L29/66 ; H01L23/535 ; H01L21/768

Abstract:
According to one embodiment, the stacked body includes a plurality of electrode layers and a plurality of insulating layers alternately stacked on the substrate. The plurality of contact parts are provided in a protruding shape on respective end parts of the plurality of electrode layers. The plurality of contact parts do not overlap each other in the stacking direction. The plurality of contact parts are displaced in a surface direction of the substrate. The plurality of plugs extends from the respective contact parts toward the respective circuit interconnections and electrically connects the respective contact parts with the respective circuit interconnections.
Public/Granted literature
- US20150069499A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME Public/Granted day:2015-03-12
Information query
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