Invention Grant
US09029988B2 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
有权
通过n +外延晶片中的硅通孔减少寄生电容
- Patent Title: Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
- Patent Title (中): 通过n +外延晶片中的硅通孔减少寄生电容
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Application No.: US13743882Application Date: 2013-01-17
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Publication No.: US09029988B2Publication Date: 2015-05-12
- Inventor: Kangguo Cheng , Subramanian S. Iyer , Pranita Kerber , Ali Khakifirooz
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Steven Meyers
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L23/04 ; H01L29/80 ; H01L23/538 ; H01L23/48

Abstract:
A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.
Public/Granted literature
- US20130127067A1 THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE Public/Granted day:2013-05-23
Information query
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