Invention Grant
- Patent Title: Three dimensional stacked structure for chips
- Patent Title (中): 芯片三维堆叠结构
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Application No.: US14147293Application Date: 2014-01-03
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Publication No.: US09030015B2Publication Date: 2015-05-12
- Inventor: Tsai-Yu Huang , Yi-Feng Huang
- Applicant: Tsai-Yu Huang , Yi-Feng Huang
- Agency: Huntington IP Consulting Co., Ltd.
- Agent Chih Feng Yeh
- Priority: TW102100320A 20130104
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/522 ; H01L21/66

Abstract:
A 3-D chip stacked structure is disclosed. Each chip layer is provided with plural single-layered conductive members where among the same chip layer the two adjacent conductive members are structurally formed in mirror symmetric way with each other along a chip longitudinal direction and the arrangements of the single-layered conductive members of the two adjacent chip layers are shifted by a test pad distance. The single-layered conductive members of the two adjacent chip layers are communicated through a vertical TSV (through silicon via). Therefore, a selection signal or an enabling signal might be transferred through this specific metal layer and related TSV to reach targeting chip layer and targeting circuit.
Public/Granted literature
- US20140191234A1 Three Dimensional Stacked Structure for Chips Public/Granted day:2014-07-10
Information query
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