An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.