Invention Grant
- Patent Title: Stack type semiconductor circuit with impedance calibration
- Patent Title (中): 具有阻抗校准的堆叠型半导体电路
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Application No.: US13845628Application Date: 2013-03-18
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Publication No.: US09030026B2Publication Date: 2015-05-12
- Inventor: Sang Jin Byeon
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2012-0147438 20121217; KR10-2012-0150166 20121221
- Main IPC: H01L23/64
- IPC: H01L23/64 ; G01R31/28 ; H01L25/065
Abstract:
A stack type semiconductor circuit includes a plurality of semiconductor chips stacked therein, wherein the plurality of semiconductor chips are configured to share impedance calibration information. The plurality of semiconductor chips include at least one resistance value of an external resistor and an impedance calibration signal as the impedance calibration information.
Public/Granted literature
- US20140167281A1 STACK TYPE SEMICONDUCTOR CIRCUIT WITH IMPEDANCE CALIBRATION Public/Granted day:2014-06-19
Information query
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