A duty-cycle modulated bit signalling method and circuit, comprising: signaling bits by virtue of a duty-cycle ratio; wherein the duty-cycle ratio is varied dependent upon the transmission rate of the signalling. A bit period comprises a long phase and a short phase and the duty-cycle therebetween is varied such that the ratio between the duration of the long phase and the duration of the short phase is increased for decreasing transmission rate. The duty-cycle ratio is varied dependent upon the transmission rate of the signalling according to one or more ranges of transmission rate. In a higher transmission rate range the duty-cycle is defined as a fixed ratio, and in a lower transmission range the duty-cycle is defined by a fixed length of the short phase of the bit period.