Invention Grant
- Patent Title: Parallel bit interleaver
- Patent Title (中): 并行位交织器
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Application No.: US14116608Application Date: 2012-05-18
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Publication No.: US09032260B2Publication Date: 2015-05-12
- Inventor: Mihail Petrov
- Applicant: Mihail Petrov
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: EP11004126 20110518
- International Application: PCT/JP2012/003260 WO 20120518
- International Announcement: WO2012/157282 WO 20121122
- Main IPC: G06F11/00
- IPC: G06F11/00 ; H03M13/00 ; H03M13/27 ; H03M13/11 ; H03M13/25 ; H03M13/29 ; H03M13/35 ; H04L1/00

Abstract:
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.
Public/Granted literature
- US20140126674A1 PARALLEL BIT INTERLEAVER Public/Granted day:2014-05-08
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