Invention Grant
US09032348B2 Physics-based reliability model for large-scale CMOS circuit design
有权
基于物理的大规模CMOS电路设计可靠性模型
- Patent Title: Physics-based reliability model for large-scale CMOS circuit design
- Patent Title (中): 基于物理的大规模CMOS电路设计可靠性模型
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Application No.: US14100712Application Date: 2013-12-09
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Publication No.: US09032348B2Publication Date: 2015-05-12
- Inventor: Hugh James Barnaby , Ivan Sanchez Esqueda
- Applicant: Arizona Board of Regents on behalf of Arizona State University , University of Southern California
- Applicant Address: US AZ Scottsdale US CA Los Angeles
- Assignee: Arizona Board of Regents on behalf of Arizona State University,University of Southern California
- Current Assignee: Arizona Board of Regents on behalf of Arizona State University,University of Southern California
- Current Assignee Address: US AZ Scottsdale US CA Los Angeles
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.
Public/Granted literature
- US20140165017A1 PHYSICS-BASED RELIABILITY MODEL FOR LARGE-SCALE CMOS CIRCUIT DESIGN Public/Granted day:2014-06-12
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